1. Field of the Invention
This invention relates to digital processing and testing techniques, and more particularly to control of addresses and data stored in a memory device.
2. Background of Related Art
Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a xe2x80x9ccodec.xe2x80x9d A codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from Pulse Code Modulation (PCM) digital signals.
Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality audio capability, today""s codecs find practical application in consumer stereo equipment including CD players, modems, computers and digital speakers.
With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. Improved S/N ratios have been achieved largely by separating the conventional codec into two individual sub-systems and/or two separate integrated circuits (ICs): a controller sub-system handling primarily the digital interface to a host processor, and an analog sub-system handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented most recently as the xe2x80x9cAudio Codec ""97 Component Specificationxe2x80x9d, Revision 1.03, Sept. 15, 1996, as revised in xe2x80x9cAudio Codec ""97xe2x80x9d, Revision 2.0, Sep. 29, 1997 (collectively referred to herein as xe2x80x9cthe AC ""97 specificationxe2x80x9d). The AC ""97 specification in its entirety is expressly incorporated herein by reference.
FIG. 1 is a generalized block diagram of a conventional split-architecture audio codec conforming to the AC ""97 specification. Audio codecs conforming to the AC ""97 specification accommodate audio sources from CD players, auxiliary devices such as stereo equipment, microphones and/or telephones.
As shown in FIG. 1, currently known split-architecture audio codecs contemplate a host processor, an audio codec (AC) controller sub-system or IC 402, and an AC analog sub-system or IC 404. The connection between the AC controller sub-system 402 and the AC analog sub-system 404 is currently defined as a five-wire time division multiplexed (TDM) interface controlled by an AC-link 406 in the AC analog sub-system 404. The AC controller sub-system 402 may be a stand alone device, or it may be a portion of a larger device such as a Peripheral Component Interconnect (PCI) interface device. PCI is a processor-independent, self-configuring local bus. Alternatively, the AC controller sub-system 402 may be a part of a central processing unit (CPU).
Because of the capabilities of the split digital/analog architecture (i.e., AC controller sub-system 402 and AC analog sub-system 404), the AC ""97 specification includes a significant amount of flexibility intended to capture a large market by satisfying many consumer-related audio needs. For instance, the conventional AC analog sub-system 404 includes interface capability to accept input from multiple sources and to mix the analog signals from those multiple sources. Possible analog signal sources include a CD, video, or telephone line.
FIG. 2A is a diagram showing relevant features of the conventional AC analog sub-system 404. The relevant features include an analog mixing and gain control section 200 accepting input from various analog audio sources 210 including a PC Beep signal, a telephone input, two microphone inputs, a general line in, a signal from a CD player, an analog signal from a video source, and an auxiliary input. The analog mixing and gain control section 200 mixes analog signals input from the various analog audio sources 210, and outputs up to three separate analog channels for digitization in analog-to-digital (A/D) converters 206a, 206b, 206c. A digital interface 202 prepares the mixed, digitized audio signals output from the A/D converters 206a-206c into a serial data stream for transmission via an AC link 406.
In the opposite direction, digital audio signals received from the serial data stream of the AC link 406 by the digital interface 202 are converted back into analog audio signals by digital-to-analog (D/A) converters 204a, 204b, and output to the analog mixing and gain control section 200 for gain control and output on the various desired analog audio source lines 210.
FIG. 2B is a more detailed schematic diagram of the analog mixing and gain control section 200 of the AC analog subsystem 404 shown in FIG. 2A. In FIG. 2B, the analog signals from the analog audio sources 210 are gain adjusted in analog form by analog gain adjusters 300, then mixed in analog mixer 310. A secondary analog mixer 312 allows the inclusion of the PC beep signal and telephone signal into the mixed analog product. The mixed analog signal is gain adjustable in gain adjuster 302 and output from the Analog mixing and gain control block 200 and AC analog subsystem 404. Analog mixer 314 mixes the left and right channels of the summed analog signal to provide a mono signal output, which is gain adjusted in analog gain adjuster 304. Analog mixer 316 similarly provides a mono output from the stereo output signal.
For recording, a multiplexer (MUX) 320 multiplexes signals from the various sources and allows selection of one per channel of the various sources together with a microphone signal for output to a master analog gain adjuster 306. The three gain adjusted analog signals output from MUX 320 are finally converted into digital signals by A/D converters 206a, 206b and 206c. Thus, the mixing and gain control of a conventional AC analog subsystem 404 is typically handled with analog circuitry.
While it is suitable to mix and gain adjust audio signals in analog form for certain applications as shown in FIGS. 2A and 2B, analog features on an integrated circuit require significant amounts of space in the AC analog subsystem 404. Analog circuitry also generally provides a larger source of electrical noise causing cross-talk or other disadvantageous side effects. Thus, to improve a signal to noise ratio of output signals, it is desirable to provide digital testing and processing techniques, e.g., to minimize the analog circuitry in the AC analog subsystem.
In accordance with the principles of one aspect of the present invention, an address generator for a memory device comprises an adder. A non-sequential counter inputs a non-sequential sequence of numerical data to a first input of the adder, and an output latches an output of the adder as an address for the memory device.
In another aspect, an address generator comprises adder means for adding at least two input data samples. Non-sequential counting means provides a non-sequential sequence of numerical data to a first input of the adder means, and an output latch means latches an output of the adder means as an address for the memory device.
One method of generating an address for a memory device in accordance with one aspect of the present invention comprises providing a non-sequential sequence of numerical data. One of the non-sequential sequence of numerical data is latched and added to a current one of the non-sequential sequence of numerical data to provide an address for the memory device.
In accordance with another aspect of the present invention, apparatus is provided to reset data in a memory device. The apparatus comprises a write control module adapted to control write cycles to the memory device. A latch, held in a reset condition while the first frame signal is being provided, provides input data to the memory device. A first frame detector provides a first frame signal substantially during a duration of a first frame of data.
A method of resetting data in a memory device in accordance with the present invention comprises providing a latch in communication with a data input of the memory device. Repeatedly, for each of a plurality of addresses applied to the memory device, the latch is held in a reset condition, the address is provided to an address input of the memory device, and a write control signal is provided to the memory device.